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Sverres home Introduksjon SW development projects: Programmeringsprosjekt (Flere oppgaver) Nye kart-tavler for D-blokka Elevator automatic FAT for TTK4145 Procedural Generation: Game Worlds Procedural Generation: Music Programvare design av simulator Dynamic deployment system for real-time tasks Measurement-based real-time system Bibliotek for meldingssending Teoretical projects: Deterministic execution of Lingua Franca on emulated RISC-V hardware Implementing Lingua-Franca programs on real-time operating systems Models of Computation Salvaging XC features Schedulability proof for message passing systems Dynamic deployment system for real-time tasks Bruk av online eksekveringstidsestimater Real-time systems not based on timing requirements Programering av tunge tråder ved nonpreemptive scheduling. Deling av CPU og Nettverk Morsomme sensorer og applikasjoner: Døvehørsel Blindesyn Bike trainer app Eksterne oppgaver: |
Deterministic execution of Lingua Franca on emulated RISC-V hardware
This project aims to validate the deterministic execution of software on small emulated RISC-V embedded platforms. A Lingua Franca program should be developed and compiled for a RISC-V target and evaluated using such an emulated environment. Ideally, the project will lead to a master’s thesis where the work started in this project is continued and evaluated on physical hardware. One expected outcome of this project is to plan and describe the content of such a master’s thesis. Background and motivationCyber-physical systems continue to expand into safety-critical systems such as automotive, medical, industrial, and more. In such systems, deterministic execution is essential yet remains elusive, and the number of variables directly and indirectly affecting execution order remains high. RISC-V is an open-source RISC instruction set architecture (ISA). It is designed to be simple, modular, and extensible, providing design freedom. This makes RISC-V an interesting platform for small IoT and CPS applications, especially in the low-power spectrum. The open license and extensibility make RISC-V an interesting choice for specialized systems, which is a good fit for CPS. Lingua Franca (LF) is a coordination framework that ensures the deterministic execution of time-sensitive, concurrent, and distributed software. In LF, a program is composed of reactors, which are concurrent, stateful, and event-triggered objects communicating via ports. Reactors can be executed on single cores or multi-cores or distributed over a network while retaining the same deterministic semantics. This enables developers to write concurrent, distributed programs where logical time and causality are explicitly managed. LF is ideal for CPS, robotics, and other real-time embedded software. The promise of RISC-V in CPS, in combination with the determinism of LF, makes this an increasingly important topic. Project objectives1. Define a test methodology for measuring and asserting deterministic behavior for a small test application using LF primitives. 2. Use Renode or Qemu to start an emulated environment for a RISC-V quad-core system (PolarFire), modify the base system, and verify the updated kernel/filesystem. 3. Cross-compile and run a test application in the RISC-V environment. 4. Port a small LF application to RISC-V and evaluate execution on target.Tools and platformsTools and platformsRenode emulator / Qemu PolarFire SoC (BeagleV Fire) Linuga Franca development environment RISC-V GCC toolchainExpected project outcomes1. A state-of-the-art (SotA) analysis of deterministic software and hardware available, and where RISC-V and LF fit into this. 2. A test methodology tailored to work with an emulated environment and physical hardware. Criteria must be decoupled from physical time and rather measure execution order. 3. A clear and reproducible step-by-step approach for creating a new environment for either Renode or PolarFire kit and instructions for effectively uploading new test binaries to the target environment. 4. An initial test application that will run on the emulated system / target hardware to show how software can be cross-compiled and uploaded to the target. 5. A plan detailing tasks and challenges to be overcome in a master’s thesis project and how to expand lessons learned into a deeper project.SupervisionSupervisor: Sverre Hendseth sverre.hendseth@ntnu.no Co-supervisor: Henrik Austad henrik.austad@sintef.no (SINTEF Digital, Department of Mathematics and cybernetics, Reliable Automation) Co-supervisor/advisor: Erling R. JellumThe place of work will be either ITK or a suitable office at RA. RA will provide an evaluation kit (BeagleV Fire). The student is expected to bring their own laptop. The necessary software and tools are open-source and freely available. |